1. Technical Field
The present invention relates to semiconductor structures and fabrication methods, and in particular to functional structures formed with metal interconnects on a same layer and methods for fabricating the same.
2. Description of the Related Art
Typical conventional integration schemes for forming electrical contacts for transistors in a semiconductor chip include depositing a nitride stop layer on top of finished front end of line (FEOL) devices (e.g., transistors). An oxide layer is deposited and planarized. Contact patterns are formed by lithography on a regular resist, resist on antireflection coating (ARC) mask stacks or multiple layer mask stacks, such as a tri-layer mask stack, which need to be removed in later steps. Plasma etch processes are used to transfer the contact patterns into the oxide layer by opening the ARC layer, etching through the oxide layer, which typically has a different thickness on the top of gate and source/drain areas of the transistors, and then stopping on the nitride stopping layer. The nitride stopping layer is etched through—stopping on silicide layers on top of the gate and source/drain areas.
Current integration schemes and process flows for contact formation etch contact holes and stop on top of the gates and on the top of silicides in the source/drain area. These structures include only conductive materials for forming interconnects between adjacent layers.